dd86k's blog

Machine code enthusiast

Development Progress 2021 Q4

Author: dd
Published: November 27, 2021
Last modified: May 20, 2023 at 13h44
Categories:

Hello! This will be the last quarterly report as I will be moving to monthly reports starting 2022.

A lot can happen in a quarter of a year, right?

sha3-d

Version 1.1 was released to fix usage with the OOP Digest wrapper.

Version 1.2 planned to have much better optimizations. Like using the intel-intrinsics package. Or make SHAKE using a configurable digest size.

ddh

Version 1.2 was released to support SRI-styled hashes via the --sri switch.

SRI hashes can be useful for CDN to validate the integrity of the file downloaded. A SRI sting is made up of a hash type and its result in the base64 format.

For example, a hash of sha256-8wutfx+KBoW3mIllMdYNBGHlIVe39Umu94JjV3VdYOs= indicates that the sha256 hash result must result in f30bad7f1f8a0685b798896531d60d0461e52157b7f549aef7826357755d60eb in binary for the file. (It is funny that the hash contains “bad” too)

Version 1.3 planned to have support for BLAKE2 (p and b variants).

ddhx

Version 0.3.2 and version 0.3.3 were released to add stdin support in interactive mode.

It’s now possible to do things like:

echo LICENSE | ddhx

Version 0.4 planned to have some form of type-aware system. I think.

ddcpuid

Version 0.19 adds a new physical core count, a revamped Summary view alongside a Detailed view, and better cache topology.

The new Summary view now looks like this:

Name:        GenuineIntel Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
Identifier:  Family 0x6 Model 0x3a Stepping 0x9
Cores:       4 cores 8 threads
Max. Memory: 64GB physical 256TB virtual
Techs:       x86-64-v2 EIST TurboBoost Intel-TXT/SMX HTT
SSE:         SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2
AVX:         AVX
AMX:         None
Others:      AES-NI
Mitigations: IBRS STIBP SSBD L1D_FLUSH MD_CLEAR
Cache L1-D:  4x 32KB    (128KB)  SI
Cache L1-I:  4x 32KB    (128KB)  SI
Cache L2-U:  4x 256KB   (1MB)    SI
Cache L3-U:  1x 8MB     (8MB)    SI CI CCI

To kind of compete (per say) with cpuid(1), I introduced the -d and --detailed switches for the Detailed view that looks like so:

Vendor      : GenuineIntel
Brand       : Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
Identifier  : 0x306a9
Family      : 0x6
BaseFamily  : 0x6
ExtFamily   : 0x0
Model       : 0x3a
BaseModel   : 0xa
ExtModel    : 0x3
Stepping    : 0x9
Cores       : 4
Threads     : 8
Extensions  : x87/FPU +F16C MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 Intel64/x86-64 +LAHF64 VT-x/VMX AVX AES-NI
Extra       : MONITOR+MWAIT +MIN=64 +MAX=64 PCLMULQDQ CMPXCHG8B CMPXCHG16B RDRAND RDMSR+WRMSR SYSENTER+SYSEXIT SYSCALL+SYSRET RDTSC +TSC-Deadline +TSC-Invariant RDTSCP CMOV FCOMI+FCMOV POPCNT XSAVE+XRSTOR XSETBV+XGETBV FXSAVE+FXRSTOR
Technologies: EIST TurboBoost Intel-TXT/SMX HTT
Cache       : CLFLUSH=64B SS
Level 1-D   : 4x    32 KB, 8 ways, 1 parts, 64 B, 64 sets SI
Level 1-I   : 4x    32 KB, 8 ways, 1 parts, 64 B, 64 sets SI
Level 2-U   : 4x   256 KB, 8 ways, 1 parts, 64 B, 512 sets SI
Level 3-U   : 1x  8192 KB, 16 ways, 1 parts, 64 B, 8192 sets SI CI CCI
ACPI        : ACPI APIC x2APIC ARAT TM TM2 APIC-ID=0 MAX-ID=16
Virtual     : VME
Memory      : PAE PSE PSE-36 Intel-XD/NX PAT MTRR PGE SMEP
PhysicalBits: 36
LinearBits  : 48
Debugging   : MCA MCE DE DS DS-CPL DTES64 PDCM PBE
Security    : IBRS STIBP SSBD L1D_FLUSH MD_CLEAR
Max. Leaf   : 0xd
Max. V-Leaf : 0x0
Max. E-Leaf : 0x80000008
Type        : Original
Brand Index : 0
Misc.       : xTPR PCID FSGSBASE

If, I guess, at least one person asks for it, I could do a JSON output, because this detailed view doesn’t seem very “parsable”.

Version 0.20 planned maybe to be able to dump and load cpuid results. And Alder Lake hybrid support, maybe?

alicedbg

Sadly, I got lazy and didn’t get to finish 0.1 for September as planned. Maybe 2022 Q3 at best at this slow pace.

Everytime I open up the x86 decoder, I get scared, but I have a plan to use a mix of bitflags, templates, and switches. So it’s hopeful?

I did adjust the risc-v decoder up to standard so it can process rv32 a little:

$ alicedbg -D --raw -march rv32 examples/o/riscv32-none-elf.bin
       0  1141                    addi        sp, sp, -0x10
       2  c622                    sw          s0, 0xc(sp)
       4  0800                    addi        s0, sp, 0x10
       6  0793 0380               li          a5, 0x38
       a  853e                    mv          a0, a5
       c  4432                    lw          s0, 0xc(sp)
       e  0141                    addi        sp, sp, 0x10
      10  8082                    ret
      12  1101                    addi        sp, sp, 0x0
      14  ce06                    sw          ra, 0x1c(sp)
      16  cc22                    sw          s0, 0x18(sp)
      18  1000                    addi        s0, sp, 0x20
      1a  37dd                    jal         -0x1a
      1c  872a                    mv          a4, a0
      1e  0793 0a40               li          a5, 0xa4
      22  8f99                    sub         a5, a5, a4
      24  2623 fef4               sw          0xfef(s0), a5
      28  0001                    nop
      2a  40f2                    lw          ra, 0x1c(sp)
      2c  4462                    lw          s0, 0x18(sp)
      2e  6105                    (bad)
      30  8082                    ret

While the decoder is imperfect, it does still work with the Intel syntax:

$ alicedbg -D --raw -march rv32 -syntax intel examples/o/riscv32-none-elf.bin
       0  1141                    addi        sp, sp, -0x10
       2  c622                    sw          s0, dword ptr [sp+0xc]
       4  0800                    addi        s0, sp, 0x10
       6  0793 0380               li          a5, 0x38
       a  853e                    mv          a0, a5
       c  4432                    lw          s0, dword ptr [sp+0xc]
       e  0141                    addi        sp, sp, 0x10
      10  8082                    ret
      12  1101                    addi        sp, sp, 0x0
      14  ce06                    sw          ra, dword ptr [sp+0x1c]
      16  cc22                    sw          s0, dword ptr [sp+0x18]
      18  1000                    addi        s0, sp, 0x20
      1a  37dd                    jal         -0x1a
      1c  872a                    mv          a4, a0
      1e  0793 0a40               li          a5, 0xa4
      22  8f99                    sub         a5, a5, a4
      24  2623 fef4               sw          dword ptr [s0+0xfef], a5
      28  0001                    nop
      2a  40f2                    lw          ra, dword ptr [sp+0x1c]
      2c  4462                    lw          s0, dword ptr [sp+0x18]
      2e  6105                    (bad)
      30  8082                    ret

Maybe huge projects aren’t my thing after all, or I was simply a little too ambitious.

Not giving up on this, but sometimes it gets a little difficult.

DDPBX

While I don’t exactly keep track of development for this project, I’ll try to enumerate changes done.

Directory applications were added for the PBX and exchange branch.

Two Four new tracks were added to the Music On Hold list.

A TTS function was introduced using the CMU Flite (Festival Lite) engine and its default voice, kal, that someone pointed out sounds like DECtalk. Unfortunately, while the kal16 voice sounds much better, it output 16000Hz RIFF audio files, of which Asterisk complains about (but not 8000Hz RIFF audio files). Converting it on the go kind of destroys the purpose of using flite, because the different between festival and flite saves around 250ms of processor time (and using ffmpeg on top of that won’t help). But I might see what I can do about that.

With that, I added what I call a Fortune Teller at 077-386-9910. This calls fortune(1) (default settings, without the offensive maxims) and plays it back via the TTS function. After that, the system asks if you want another adage. Fun!